Maximum-Likelihood Stereo Correspondence using Field Programmable Gate Arrays

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Typical software approaches tend to be too slow for real time performance on high frame rate (≥ 30fps) stereo acquisition systems. Hardware implementations of these same algorithms allow for parallelization, providing a marked improvement in performance. This paper will explore one such hardware implementation of a maximum-likelihood stereo correspondence algorithm on a Field Programmable Gate Array (FPGA). The proposed “FastTrack” hardware implementation is a first stage prototype that demonstrates comparable results to equivalent software implementations. Future optimizations will have the added advantage of high-speed (up to 200fps) and motion-compensated stereo depth estimation.